As integrated circuit geometries shrink, the relationships between the individual elements of the circuits also tend to change. This situation tends to create pressure in two different areas. First, the individual elements themselves need to be fashioned according to smaller geometries, so as to support the overall reduced size of the integrated circuit. Second, the processes used to form the individual elements may need to be adjusted, as the traditional processing methods may have detrimental effects on the other elements of the integrated circuit, that are likewise smaller and more easily effected by adjoining elements and the other processes used to form the integrated circuit.
For example, in deep submicron CMOS devices, it is desirable to form gate electrodes with a thinner layer of material than that which is used for larger devices. However, as the thickness of the gate electrode is reduced, the conductivity of the gate electrode also tends to be reduced. This tends to reduce the efficiency of the gate electrode, which impacts the speed and other aspects of the device. In addition, the reduction in the overall amount of dopant in a thinner gate electrode tends to cause carrier depletion at the interface between the gate electrode and the gate dielectric. This situation additionally effects the ability of the device to perform.
As a further example, the gate electrodes of a deep submicron CMOS device are preferably spaced at reduced distances one from the other, in support of the overall reduced device geometry. However, the reduced distances between adjacent polysilicon gates tends to make them more difficult to fabricate. One reason for this is that one gate electrode over a complementary device may be oppositely doped in relation to another gate electrode over an adjoining complementary device. Before patterning the gate electrode layer, the reduced distance between the oppositely doped regions of the gate electrode layer tends to allow the dopants to diffuse into the adjoining regions. This tends to reduce or even destroy the intended effect of the dopants in the gate electrode regions, resulting in a degradation of the integrated circuit.
What is needed therefore, is a system whereby thin and closely spaced doped layers, such as polysilicon gate electrodes in deep submicron CMOS devices, have sufficient conduction and charge delivery properties.